Ideas for next generation N8VEM SBC

            Critical (defects affecting functionality only)

                        CPU clock signal on ECB bus pin C29

                        implement IOR/IOW/MER/MEW (qualify all reads and writes)

                        Fix IEI/IEO (is it broken?)

                        increase clearance around power connector

                        Allow disabling of lower 32K RAM page 

                        Allow memory reads/writes on ECB

                        room for ZIF sockets for ROM

                        increase separation between parallel and serial connectors

 

 

            Improvements (Nice to have but can live without)

                        ground inputs on unused gates

                        change pullup resistors to 4.7K

                        Add fill zone regions on PCB

                        Add VCC to parallel connector

                        Jumper for /WR on ROM socket for FLASH memories

                        DS1210 battery backed SRAM

                        Jumpers for 24, 28, and 32 pin ROM chips

                        Jumpers for 24, 28, and 32 pin RAM chips

                        Change serial to use RTS/CTS handshaking vs. DTR/DTS

                        Diagnostic LED (attach to unused UART output or 74LS574 pin)

                        add jumper for interrupt interface for PPI

                        integrate Juha's system timer UART, RI circuit

                        export unused 74LS125/74LS574/74LS273 pins to header

                        POR improvements (new R C values, POR chip, etc)

                        add 300 mil socket pads under RAM socket

                        Use PCB RJ-45 for connectors to serial cable rather than dual row header

 

 

            Reduce PCB space

                        use half can oscillators

                        use PLCC for CPU,  UART, and PPI

                        replace 74LS14 with 74LS05+pull up resistors, eliminate Q1

 

 

            Investigate

                        using Z180 or eZ80 CPU

                        Integrating priority interrupts with UART and PPI

                        Making 8MHz default CPU clock (simplifies FDC operations)

                        using KIO rather than PPI/UART

                        Integrating SBC and ECB backplane

                        widen gap between resistor pins

                        larger diameter holes for reset switch

                        use only 64K SRAM and 32K Flash ROM on SBC

                        make all extended SRAM/EPROM on ECB peripheral memory drive

 

Ideas for the ECB bus monitor

• fix missing VCC and GND traces on U13, U11, and U5
• remote switch for single step mode
• increase pin spacing on D1
• increase pin spacing on C1

 

Ideas for the ECB backplane

• use standard backplane spacing (need to know what that is)

 

Ideas for the ECB Prototyping board

 

Ideas for the Disk IO board

 

Ideas for 6809 host processor board

• change /RESET to RESET on 8255 interface (requires cut and jumper)