Hi All!
Tonight I started on the Zilog Peripherals board. It will have a CTC, DART, and two PIOs. This board should when done provide us with much needed dual serial with full hardware handshaking (DTR/DTS and RTS/CTS), 32 pins of discrete parallel IO, and a four system timers.
All I have so far is the schematic which is in an early form. Due to some uncertainties about the design and the N8VEM system I am going to be building a hardware prototype to ensure this design works.
My friend Rolf provided an example circuit from an article in C’T Projekt which I am using as a guide. However, I am making some minor modifications to simplify the circuit a bit and to make it more compatible with the ECB Prototyping Board which I’ll use to build the hardware prototype.
You can see the article here on Rolf’s excellent ECB website. Rolf is *the* authority on ECB so we know this is good stuff. Please review the article and let me know if you have any comments or questions.
http://www.hd64180-z80180.de/assets/download2008/dart_sio_ct8504.zip
If anyone would do a scan, OCR, and translate to English I would much appreciate it. Google Translate can usually do a good enough job I can understand it.
I recall several requests for such a peripheral board since the beginning of the project. This board should satisfy many shortcomings of the system namely lack of serial IO, parallel IO, and system timer. Also it reduces the effect of the various oddities associated with the 16C550 and 82C55 IO devices on the SBC itself.
We are a long ways from seeing actual hardware but I thought it would be good for the builders to know I am finally starting on this project. Thanks to James and many others taking on the Propeller Terminal Board (what is your projects name again?) I am free to work on this other project which is also needed.
Thank you very much! I am honored to work with such a great group of home brew computer hobbyists!
Thanks and have a nice day!
Andrew Lynch
Zilog Peripherals
---------------------
Important note for those following along the Zilog Peripherals development from Bryan
YOU MAY NEED TO ADD THIS BIT OF CCT TO ENSURE THE MODE 2 INT WORKS ON THE
PIO/CTC/S ECT, WITHOUT IT THE SYSTEM UNRELIABLE
This leads to some discussion on the N8VEM forum to address the fundamental question of whether the Zilog Peripherals require *the* system CPU clock or *a* clock. It turns out that there is a need for the Zilog Peripherals to be synchronized with the CPU for correct interupt mode 2 operation.
As a result, I have modified my approach to design the Zilog Peripherals board to change the SBC to export the CPU clock signal on the ECB for use by peripheral boards. The modifications to the N8VEM SBC board are minor; just connect a simple jumper between the 4MHz TTL oscillator pin 8 and pin C29 of the ECB.
Bryan's original point is valid however I now better understand his concern now that the local vs. CPU clock appears resolved. Certainly propagation delays between the SBC and the Zilog Peripherals board through the ECB bus will be noticable and would affect timing.
Comments (0)
You don't have permission to comment on this page.